RadiSys 6200plus Series Manual de usuario Pagina 25
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Valorado. / 5. Basado en revisión del cliente
Chapter 2
Installation
2-3
T
able 2.A
SW1
Set of Switches
Switches 1-6 Switch 7 Switch 8
DH+ station number for channels
1A and 0 (see Table 2.B)
Unused (off) Memory protect.
If on, RAM memory protect is enabled.
T
able 2.B
Station
Numbers SW1 (Switches 1-6)
Station
N mber
LSD MSD
Number
(Octal)
1
2 3 4 5 6
0 on on on on on on
1 off on on on on on
2 on off on on on on
3 off off on on on on
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77 off off off off off off
Table 2.C and Table 2.D describe the switch settings for SW2.
T
able 2.C
SW2
Set of Switches
Switches 1-3 Switch 4 Switch 5 Switch 6 Switch 7 Switch 8
A16 address range of the
configuration registers.
See Table 2.D.
If on, the processor functions as the VMEbus
system controller, and no other VME cards
should attempt to be the system controller.
Important: The PLC-5/VME processor must
be in the left-most slot of the VME chassis.
See page 3-1 for a description of the
system controller.
Unused
(off)
VMEbus request level.
If switch 4 is OFF, switch 6 on defines
the bus request level as 3. If switch 6
is OFF, the bus request level is 1.
If switch 4 is ON, the bus request
level is 3 independent of the setting
of switch 6.
Unused
(off)
1
Unused
(off)
Important: Switch 6 is meaningful only if switch 4 is off.
1
SW2,
position 7,
now
controls whether the PLC-5 processor makes a VME self-reference in its POST test. If you set SW2, position 7 to OFF (up position), then the VME will make
self-references as it did before series C, revision K. If you set SW2, position 7 to ON (down position), then the POST test will skip all VME self-references, causing the following ef
fects:
– The PLC-5 processor cannot test its bus-master hardware.
– The PLC-5 processor cannot determine its own unique logical address and assumes its ULA is F0H regardless of how you set SW2, positions 1–3.
– The VME status file ULA field (word 1, bits 3-15) will always contain 000, regardless of how you set SW2, positions 1–3.
- PLC-5 VME 1
- Programmable 1
- Controllers 1
- Allen-Bradley 1
- Important User Information 2
- Table of Contents 3
- Figures/Tables 7
- Summary of Changes 8
- Using this Manual 9
- Terms and Conventions 10
- Related Publications 11
- Overview 12
- Chapter 1 13
- System Description 15
- VMEbus Interface 17
- Compatibility with the 20
- Standard PLC-5 Processor 20
- TV Processor 20
- Comparison 21
- Compliance to 23
- European Union Directives 23
- Handling the Processor 24
- Setting the Switches 24
- Chapter 2 25
- Configuring 26
- the VME 26
- Backplane Jumpers 26
- Inserting 27
- the Processor 27
- Grounding 27
- Determining Power-Supply 28
- Requirements 28
- Connecting to Remote I/O 28
- Prepare the Cable 29
- Make Remote I/O Connections 29
- Terminate the Link 30
- Connecting an Extended 32
- Local I/O Link 32
- Connecting a DH+ Link 34
- Connecting a Programming 36
- Terminal to Channel 0 36
- Installing, Removing, and 37
- Disposing of the Battery 37
- Bus-Release 40
- VME LEDs 40
- Signal Usage 41
- Device-Type Register 42
- 11111111 07 42
- Status/Control 43
- Register 43
- 11111111SLAVE BASE 44
- Commands 45
- Chapter 3 47
- Ladder-Program Interfaces 48
- Copy to VME 50
- Copy from VME 51
- Send VME Interrupt 52
- Check VME Status File 52
- Message Completion and 53
- Status Bits 53
- VME Status File 54
- Chapter 4 55
- Continuous Copy 57
- VMEbus Interrupts 58
- Continuous-Copy 63
- Notes on Copy Operations 64
- Copy Synchronization 65
- Handle-Interrupts Command 66
- Send-PCCC Command 68
- Command-Protocol 69
- Supported PCCCs 72
- Header Bit/Byte 73
- Descriptions 73
- Sample API Module 74
- Identify Host and Status 75
- Read-Modify-Write 77
- Your driver program must: 79
- The PLC-5/VME processor: 79
- Data Types 81
- Data-Type Field 82
- Example Data Types 82
- Chapter 6 86
- Example of Character String 86
- Set CPU Mode 89
- Upload All Request 90
- Memory Segment Pointers 91
- Download All Request 92
- Upload Complete 93
- Download Complete 94
- Bytes Physical 95
- Get Edit Resource 98
- Return Edit Resource 99
- Apply Port Configuration 100
- Restore Port Configuration 101
- Operation 102
- Sample API 102
- Message Format 102
- Error Codes 102
- Upload and Download 103
- Procedure 103
- PLC-5/VME Processor 104
- Communications Commands 104
- Download Procedure 105
- Performance and Operation 106
- Communication Methods 107
- Ladder-Logic Method 108
- Benchmark Tests 109
- Setup #1 110
- Setup #2 110
- Setup #3 111
- Setup #4 111
- Introduction to PLC-5/VME 112
- Processor Scanning 112
- Program Scanning 113
- I/O Scanning 116
- Discrete and Block Transfer 117
- Immediate 119
- Transferring Block Data 119
- Figure 7.4 122
- Transferring 122
- Sample Applications 123
- VMEDEMO.CPP 124
- Appendix 125
- VMEDEMO.MAK 135
- UPLOAD.CPP 137
- UPLOAD.MAK 148
- DOWNLOAD.CPP 149
- DOWNLOAD.MAK 156
- Interface Modules 159
- Appendix B 160
- COMMON.H 161
- COMMON.C 163
- UWORD statCtrlReg = 0; 173
- status); 174
- P40VCC0.H 175
- P40VCC0.C 176
- P40VHINT.H 190
- P40VHINT.C 191
- P40VSPCC.H 197
- P40VSPCC.C 198
- P40VWBP.H 201
- P40VWBP.C 202
- P40VAPC.H 204
- P40VAPC.C 205
- P40VULC.H 207
- P40VULC.C 208
- P40VDLA.H 210
- P40VDLA.C 211
- P40VDLC.H 213
- P40VDLC.C 214
- P40VECHO.H 216
- P40VECHO.C 217
- P40VGER.H 219
- P40VGER.C 220
- P40VIHAS.H 222
- P40VIHAS.C 225
- P40VRBP.H 227
- P40VRBP.C 228
- P40VRER.H 230
- P40VRER.C 231
- P40VRMW.H 233
- P40VRMW.C 234
- P40VRPC.H 238
- P40VRPC.C 239
- P40VSCM.H 241
- P40VSCM.C 242
- P40VULA.H 244
- P40VULA.C 245
- Specifications 247
- VMEbus Specifications 248
- PLC-5/VME 249
- Processor Specifications 249
- Troubleshooting 250
- Appendix D 251
- Response-Word 252
- PCCC Command 252
- Status Codes 252
- Avoiding Multiple 254
- Watchdog Faults1 254
- Inserting Ladder Rungs at 254
- Cable Connections 256
- Appendix E 257
- IBM PS/2 Model 30 259
- IBM PS/2 Model 60 259
- 1784-T47 259
- 25-Pin Serial Port 259
- 9-Pin Serial Port 260
- Cable Pin Assignments 261
- Cable Specifications 262
- See also 272
- With major offices worldwide 275
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