RadiSys EPC-2 Especificaciones Pagina 86

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EPC-7 Hardware Reference
IF SBER is asserted by itself, then a BERR response occurred to one of the VME
accesses. If both SBER and VXR bits are asserted, then the checking described in
point 1 must be followed to determine the source of the VXR.
Two conditions generate hardware resets that include resetting all of the hardware.
One is receipt of VME SYSREST with bit SRIE set. The other is expiration of the
watchdog timer period, when bit WDA is set (meaning that one wants the watchdog
timer to generate a reset rather than an interrupt).
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