RadiSys EPC-8A Especificaciones

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EPC-3305 Hardware ReferenceviiiFiguresFigure 1-1. The EPC-3305...

EPC-3305 Hardware Reference88Installing and configuring the RTMThis explains how to install the EPC-3305 in a CompactPCI chassis.Inserting the RTMTo i

Appendix E: Rear Transition module (RTM)89Removing the RTMOccasionally you may need to remove the RTM to perform maintenance tasks such as replacing t

EPC-3305 Hardware Reference90ConnectorsThis details the connectors used by the EPC-3305 RTM and gives the signal pinout of each connector.Connector lo

Appendix E: Rear Transition module (RTM)91Backplane J3The J3 connector specified in CompactPCI is a female 2mm-pitch 6 column by 19 row right angle Ha

EPC-3305 Hardware Reference92Backplane J5The back plane connector J5 routes both Ethernet channels, keybard and mouse, secondary EIDE, and PMC socket

Appendix E: Rear Transition module (RTM)93H1 (COM 1) IDE (secondary)The secondary IDE connector is a male 44-pin right-angle header located on the R

EPC-3305 Hardware Reference94Keyboard/mouseThe keyboard and mouse connector, located on the RTM’s rear panel, is a 6-pin mini-DIN defined as:Table E-6

Appendix E: Rear Transition module (RTM)95PIM (PMC I/O Module)The PIM connector, located on the RTM’s rear panel, accepts a PIM that receives rear I/O

EPC-3305 Hardware Reference96Table E-8. PIM connector pin-out: J24Pin Signal Pin Signal1I/O 2I/O3I/O 4I/O5I/O 6I/O7I/O 8I/O9I/O 10I/O11 I/O 12 I/O13 I

Appendix E: Rear Transition module (RTM)97RS-232 (COM 2)The RS-232 serial port is a male DB-9 DTE. The port is mounted on the RTM and is accessible on

ContentsixTablesTable 1-1. EPC-3305 environmental specifications... 4.T

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99F Re-programming the flash chip FThis appendix details how to update or recover your system BIOS, Flash Boot Device (FBD), and Boot Block. You accom

EPC-3305 Hardware Reference100About re-programming the flash chipOn rare occasions, part or all of the flash chip contents may require replacement. Yo

Appendix F: Re-programming the flash chip101When re-programming the flash chip, follow this process. The rest of this chapter includes detailed instru

EPC-3305 Hardware Reference102Before you begin• Ensure that you have the following:• Minimum 2 MB of DRAM to run the re-flash program• A 3.5" 1.4

Appendix F: Re-programming the flash chip103Creating a Flash Boot disketteRe-programming the flash chip requires a Flash Boot diskette that contains b

EPC-3305 Hardware Reference104Now that you have created a Flash Boot diskette, re-flash your system using the directions for the re-flash method you w

Appendix F: Re-programming the flash chip105Using phlash.exe to re-program the flash chip1. If you plan to include the Boot Block when re-programming

EPC-3305 Hardware Reference106Using BIOS configuration options to re-program the flash chip1. If you plan to re-program the Boot Block, connect the Bo

Appendix F: Re-programming the flash chip107Using jumpers to re-program the flash chip1. Install the force recovery jumper:A. Turn system power off, t

EPC-3305 Hardware ReferencexTable A-33. Interrupts...

EPC-3305 Hardware Reference108

109GlossaryAccess TimeA factor in measurement of a memory storage device’s operating speed. It is the amount of time required to perform a read operat

EPC-3305 Hardware Reference110BIOS UpdateA process whereby an existing, uncorrupted BIOS image in the flash boot device is overwritten with a new imag

Glossary111CHS(Cylinders/Heads/Sectors) A specification of disk drive operating parameters consisting of the number of disk cylinders, disk drive read

EPC-3305 Hardware Reference112FPGA(Field Programmable Gate Array) A large, general-purpose logic device that is programmed at power-up to perform spec

Glossary113microprocessor to jump to a special program called the interrupt service routine. The microprocessor executes this special program, which n

EPC-3305 Hardware Reference114PLL(Phase-Locked Loop) A semiconductor device which functions as an electronic feedback control system to maintain a clo

Glossary115RTC is typically receives power from a small battery to retain the current time of day when the computer is powered down.ReflashingThe proc

EPC-3305 Hardware Reference116SRAM(Static Random Access Memory) A semiconductor RAM device in which the data remains permanently stored as long as pow

117N A B C D E F G H I J K L M N O P Q R S T U V W X Y ZIndexNumerics32-bit I/O 17.Aaccess time, defined 109.addressesdefined 109.logical, defined 113

11 Overview The EPC-3305, a CompactPCI† Peripheral Processor Board, operates in a 6U peripheral slot of a CompactPCI system.The EPC-3305 hardware is c

EPC-3305 Hardware Reference118N A B C D E F G H I J K L M N O P Q R S T U V W X Y Zdevice configuration, I/O 24.DMA controller, I/O Map 65., 68.driver

Index119N A B C D E F G H I J K L M N O P Q R S T U V W X Y ZLLarge Disk Access Mode 25.LBA Mode Control 17.LEDs 59., 83.Local interrupt control regis

EPC-3305 Hardware Reference120N A B C D E F G H I J K L M N O P Q R S T U V W X Y ZSsecond interrupt controller 67.secondar IDE, I/O map 68., 70.seria

EPC-3305 Hardware Reference2Feature summaryThe EPC-3305 CPU board is a Pentium† III-based, PC-compatible, single slot CompactPCI computer designed for

Chapter 1: Overview3• Front Panel Interface• Blue HS LED• RJ45 for COM-1• RJ45 for Ethernet 1• Reset Button• National Semiconductor 87309 Super I/O• T

EPC-3305 Hardware Reference4Specifications 1These are system-level tests. The EPC-3305’s conformance to these specifications may be affected by the re

52 Configuration and installation This chapter explains how to install the EPC-3305 in a CompactPCI chassis.When reading this file online, you can imm

EPC-3305 Hardware Reference6Setting jumpers and headers FlashThe CPU board provides a 2x5-pin header (H2) that you use to re-program the Flash chip. F

Chapter 2: Configuration and installation7MFGThis jumper block is reserved by the board manufacturer for testing purposes.Inserting the EPC-3305You in

EPC, iRMX, INtime, Inside Advantage, and RadiSys are registered trademarks of RadiSys Corporation. Spirit, DAI, DAQ, ASM, Brahma, and SAIB are tradema

EPC-3305 Hardware Reference8• BIOS configuration (For information about setting up the BIOS configuration, see Chapter 3, BIOS configuration)• Driver

Chapter 2: Configuration and installation95. Press the new battery into place, positive (+) side up.6. Replace the EPC-3305 in the CompactPCI chassis

EPC-3305 Hardware Reference10

113 BIOS configuration The EPC-3305 uses the Phoenix NuBIOS to configure and select various system options. This chapter details the various menus and

EPC-3305 Hardware Reference12Menu mapYou set up the BIOS by making selections from the menus shown in the next table. When reading this file online, y

Chapter 3: BIOS configuration13Main Setup menu The far right menu in the menu bar is the Exit Menu. Use the options in the Exit menu to save your chan

EPC-3305 Hardware Reference14LegacyDiskette ALegacyDiskette BIdentifies the type of floppy disk drive installed as the A: or B: drive. Possible setti

Chapter 3: BIOS configuration15Primary/Secondary Master/Slave sub-menusThere are a total of four IDE adapter sub-menus for the primary and secondary h

EPC-3305 Hardware Reference16Field DescriptionType Identifies the disk type. You can select one of these:Note: You must press + and - to change this f

Chapter 3: BIOS configuration17Multi-Sector Transfers Allows the System BIOS to read ahead by the specified number of sectors during disk access. This

1Before you beginThis guide provides the information you need to install the EPC-3305 and configure its BIOS. It contains detailed hardware reference

EPC-3305 Hardware Reference18Transfer Mode Selects the mode that the System BIOS uses to access the hard disk. You can select one of these:• Standard

Chapter 3: BIOS configuration19Keyboard Features sub-menuUse this sub-menu to enable or disable various keyboard features. Figure 3-3. Keyboard Featur

EPC-3305 Hardware Reference20Keyboard auto-repeat rate Sets the auto-repeat rate when holding a key down on the keyboard.You can select one of these:•

Chapter 3: BIOS configuration21UBE Shadow Control sub-menu Use this menu to specify BIOS shadow options.Shadowing refers to the technique of copying B

EPC-3305 Hardware Reference22Field DescriptionBIOS Extension Source OffsetControls the location of the user BIOS extension to shadow. You can select o

Chapter 3: BIOS configuration23Advanced menuThis menu contains settings for integrated peripherals, memory shadow, cache, and large disk access mode.

EPC-3305 Hardware Reference24I/O Device Configuration sub-menuDisplays a menu that you use to configure peripheral devices. For more information, see

Chapter 3: BIOS configuration25Legacy USB Support Determines whether the system supports the Legacy Universal Serial Bus (USB).You can select one of t

EPC-3305 Hardware Reference26Console Redirection sub-menuOptions in this menu configure console redirection. Figure 3-6. Console Redirection sub-menu

Chapter 3: BIOS configuration27Flow Control Specifies flow control. You can select one of these:• CTS/RTS (default)• XON/XOFF• NoneConsole connection

EPC-3305 Hardware Reference2Notational conventionsThis manual uses the following conventions:• Screen text and syntax strings appear in this font.• Al

EPC-3305 Hardware Reference28I/O Device Configuration sub-menuUse the options in this sub-menu to configure the onboard serial and parallel port and d

Chapter 3: BIOS configuration29Interrupt Configures the serial port interrupt.You can select one of these:• IRQ3 (default, Port B)• IRQ4 (default, Por

EPC-3305 Hardware Reference30PCI Device Configuration sub-menuUse the options in this sub-menu to control the exclusion of the UMB region for PCI or I

Chapter 3: BIOS configuration31PCI/PNP ISA UMB Region Exclusion sub-menuThe PCI/PNP ISA UMB Region Exclusion Sub-Menu controls the exclusion of PCI an

EPC-3305 Hardware Reference32PCI/PNP ISA IRQ Resource Exclusion sub-menuThe PCI/PNP ISA IRQ Resource Exclusion Sub-Menu controls the exclusion of PCI

Chapter 3: BIOS configuration33Cache Memory sub-menuThe options in this sub-menu control the cacheability of certain memory regions and also the setti

EPC-3305 Hardware Reference34Cache Base 0–512kCache Base 512–640kDetermines how the system caches base memory in the specified area:You can select one

Chapter 3: BIOS configuration35Cache Memory Regions:A000–AFFFB000–BFFFDetermines how the system deals with specified memory blocks or shadow1 memory.

EPC-3305 Hardware Reference36Cache Memory Regions:C800–CBFFCC00–CFFFD400–D7FFD800–DBFFDC00–DFFFMemory regions.Determines how the system deals with spe

Chapter 3: BIOS configuration371Shadowing refers to the technique of copying BIOS extensions from ROM into DRAM and accessing them from DRAM. This all

Before you begin3• Other: If you purchased your RadiSys product from a third-party vendor, you can contact that vendor for service and support.About r

EPC-3305 Hardware Reference38Advanced Chipset Control sub-menuOptions in this menu control ?. Figure 3-12. Advanced Chipset Control sub-menuMainF1 He

Chapter 3: BIOS configuration39Boot menuThe Boot menu:• Specifies the order in which the system tries to boot from devices attached to the system.• Sp

EPC-3305 Hardware Reference40Exit menuUse the options in this menu to save and exit, or abandon your changes and exit to the system. Field Description

Chapter 3: BIOS configuration41Load Setup Values Resets the BIOS values to the original, default values set at the factory, before any suppliers or ot

EPC-3305 Hardware Reference42CMOS Save and Restore sub-menuUse the options in this menu to save, restore, or erase CMOS settings in the FBD (Flash Boo

434Theory of operation Chapter 4OverviewThe EPC-3305 includes these subsystems:• CPU board: A single-slot peripheral CPU which plugs into a 6U periphe

EPC-3305 Hardware Reference44OrganizationBlock diagramThe next figure shows the division and interconnection of EPC-3305 functions. These are describe

Chapter 4: Theory of operation45Memory mapThe 232 byte physical address space seen by the Intel Pentium III occupies three areas:1. From 0 to 1 MB is

EPC-3305 Hardware Reference46The Plug-and-Play ESCD is also stored in the Boot-Block FLASH device in the block addressed from FFFFA000h–FFFFBFFFh. Thi

Chapter 4: Theory of operation47The BIOS initialization software copies the ROM contents into DRAM (a process called shadowing) at addresses E0000h–FF

EPC-3305 Hardware Reference4

EPC-3305 Hardware Reference48The 443BX generates all control signals (such as ~RAS, ~CAS, ~WE, ~CS, and ~DQM) and multiplexed addresses for the SDRAM

Chapter 4: Theory of operation49controller also generates the ISA refresh cycles. The DMA controller supports two separate methods for handling legacy

EPC-3305 Hardware Reference50• Extended bank: Contains 128 bytes used as general purpose RAM. Time, calendar, and alarm can be represented in either b

Chapter 4: Theory of operation5121554 to hide subsystem resources from the host processor and to resolve any resource conflicts that may exist between

EPC-3305 Hardware Reference52Reset Control registerPrimary byte offset: DB:D8hSecondary byte offset: DB:D8h3.3V PMC siteThe CPU Board supports a two P

Chapter 4: Theory of operation53CompactPCI Hot SwapThe CPU Board can interrupt the local processor with IRQ10 on a hot swap switch event. The hot swap

EPC-3305 Hardware Reference54panel. For the Ethernet channel routed to both the front panel and J5 there is an auto detect circuit, which routes the s

Chapter 4: Theory of operation55onboard battery or the +3.3V power supply voltage can supply power and neither power source affects the other.The batt

EPC-3305 Hardware Reference56The keyboard interrupt connects to IRQ1. If enabled, the mouse interrupt utilizes IRQ12. The keyboard and mouse connector

Chapter 4: Theory of operation57Software must first write to the index register before reading or writing to the data register.Reset controllerThe EPC

vContentsChapter 1: Overview.Feature summary ...

EPC-3305 Hardware Reference58(POR) value is zero, indication hard reset. A value of one causes that reset source to generate a soft reset sequence.FP_

Chapter 4: Theory of operation59When exiting a CPU reset condition, the BIOS or application software can check the Reset Event Register to determine t

EPC-3305 Hardware Reference60next table defines the bit position to control these features. All bits are active high, with the exception of the ENUM b

Chapter 4: Theory of operation61Slot of the CompactPCI chassis.RTM_P Indicates that a Rear Transition Module is installed. It is an active low signal.

EPC-3305 Hardware Reference62types (hard, Soft, and POR). Figure 4-2 shows the memory overlay at the top of memory space. Each Flash device has its ow

Chapter 4: Theory of operation63voltage range. The global system reset provides a clean system restart whenever the system becomes unstable due to pow

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65A Chipset and I/O map This appendix contains the port I/O addresses for the address-mapped devices in the EPC-3305. As is standard for the ISA bus,

EPC-3305 Hardware Reference66Table A-4. Time/counter functionsI/O Addr Functional group R/W Usage0040 Timer/counter R/W Counter 0 count0041 R/W Counte

Appendix A: Chipset and I/O map67Table A-8. DMA page registers: Intel EX 82371EB of PC/ATI/O Addr Functional group R/W Usage0080 DMA R DMA page (reser

EPC-3305 Hardware ReferenceviFlash boot device ...

EPC-3305 Hardware Reference68Table A-13. Second (16-bit) DMA controllerI/O Addr Functional group R/W Usage00C0 DMA controller 2 R/W DMA 2 channel 4 ad

Appendix A: Chipset and I/O map69Table A-17. CPLDI/O Addr Functional group R/W Usage0180–018FCPLD R/W See Ta b l e 4 - 3 , CPLD I/O ports on page 56.

EPC-3305 Hardware Reference70x2FC R/W Modem control registerx2FD R Line status registerx2FE R/W Modem status registerTable A-22. Serial I/O (COM 2) po

Appendix A: Chipset and I/O map71x3C4 R/W Sequencer indexx3C5 R/W Sequencer datax3C6 R/WR/WVideo DAC pixel maskHidden DAC registerx3C7 RWDAC statePixe

EPC-3305 Hardware Reference72Table A-32. Serial I/O (COM 1) portI/O Addr Functional group R/W Usage3F8 COM 1 serial port RWReceiver bufferTransmitter

Appendix A: Chipset and I/O map731This I/O location is only active when bit 31 of the 443BX configuration address register is 1.Table A-38. 443BX conf

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75B Interrupts The following table shows interrupt assignments for the EPC-3305. Table B-1. InterruptsInterrupt DescriptionIRQ0 System timer (internal

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77C Connectors This appendix details the connectors on the EPC-3305 CPU board and gives the signal pinout of each connector.This product includes the

ContentsviiAppendix D: Error messages.Boot failures ...

EPC-3305 Hardware Reference78Connector locationsFigure C-1 shows the locations of the connectors on the EPC-3305’s CPU board. For information about in

Appendix C: Connectors79Backplane J3 and J5The J3 connector specified in CompactPCI is a female 2mm-pitch 6 column by 19 row right angle Hard Metric (

EPC-3305 Hardware Reference80CompactPCI J1 and J2The CompactPCI J1connector is a female 2mm-pitch 6 column by 25 row right angle Hard Metric (HM) conn

Appendix C: Connectors8116 ~DEVSEL GNDV(I/O)(2)(6)~STOP ~LOCK GND17 3.3V NC NC GND ~PERR GND18 ~SERR GND 3.3V PAR C/~BE[1] GND19 3.3V AD[15] AD[14] GN

EPC-3305 Hardware Reference82Notes:1This diagram defines the pin assignments from the front of the system chassis. All pins are medium length (level 2

Appendix C: Connectors83EthernetThe DTE RJ-45 phone jack provides support for one 10/100BASE-T Ethernet channel. RS-232 serial port (COM 1)The RS-232

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85D Error messages Boot failuresThe System BIOS attempts to display an error message on the VGA and halts when it encounters the following error condi

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87E Rear Transition module (RTM) This appendix describes the Rear Transition module (RTM), a single slot rear I/O module which connects to the backsid